The portfolio covers two related but legally independent families of patented inventions, both built around practical, hardware-enabled one-time pad (OTP) encryption — a cryptographic method that, when implemented correctly, cannot be broken by brute force or quantum computing. The portfolio has cleared USPTO 8-month security review under 35 U.S.C. §181.
Five patents covering the generation, secure transport, and storage of one-time-pad encryption keys — including true random number generation, custodial key management, and network transmission security. These technologies apply to data storage, network communications, and point-to-point wireless links such as key fobs and IoT devices. Several are implementable in software alone, without custom silicon.
A granted patent and three related pending/allowed filings covering a memory chip with on-chip encryption and key security, native-speed secure computation with multi-partition isolation, and in-circuit quantum key distribution between partitions. This family is designed to secure data at the hardware level, including isolation relevant to AI system containment.
Nine total filings across two patent families.
All utilize mathematically unbreakable encryption (information theoretic).
| Patent / Application | Description | Family | Status |
|---|---|---|---|
| US 10,984,138 B1 | Method and system for providing highly secured transportable data. | Data Security | Granted |
| US 11,108,550 B1 | Method and system for highly secured network communication. Also granted in China and Canada; Europe and Philippines applications pending. | Data Security | Granted |
| US 11,341,254 B2 | Method and system for securing data using random bits. | Data Security | Granted |
| US 11,537,728 B1 | Method and system for securing data using random bits and encoded key data. | Data Security | Granted |
| US 11,562,081 B2 | Method and system for controlling access to secure data using custodial key data. | Data Security | Granted |
| US 12,476,811 B2 | Multimodal memory chip with on-chip encryption and key security. Run the multimodal memory chip simulator → | Memory Chip | Granted |
| App. 19/364,956 | Multimodal memory integrated circuit with native-speed encrypted data processing, including AI system containment gating. | Memory Chip | Pending |
| App. 19/403,500 | Multimodal memory integrated circuit with native-speed encrypted data processing for use in unbreakable cryptography. | Memory Chip | Allowed — pending issue |
| App. 19/733,637 | Multi-tenant, multimodal memory integrated circuit with native-speed encrypted data processing for use in unbreakable cryptography. | Memory Chip | Pending |
| App. 19/635,158 | Multimodal memory integrated circuit with native-speed encrypted data processing and graceful cryptographic degradation architecture for use in unbreakable cryptography. | Memory Chip | Pending |
A sample of sectors where secure, verifiable computation is becoming a core requirement. Many other applications exist beyond what's listed here.
Co-inventor and named applicant across the full patent family. Software innovator and security systems architect with more than four decades of experience, including foundational contributions to network intrusion detection under U.S. Patent No. 5,796,942 — work later connected to federal investigative systems and technologies used in law enforcement and national security settings. President & CTO of Touch Technologies, Inc. since 1982, with prior consulting engagements for organizations including Citicorp, Boeing, and the U.S. Office of the President.
Co-inventor, physicist, and AI safety researcher recognized with the Future of Life Institute's 2024 lifetime achievement award. Holds degrees in physics and mathematics from Stanford and a Ph.D. in physics from U.C. Berkeley; was a computer science professor at the University of Illinois at Urbana-Champaign. Founder of Self-Aware Systems and, currently, Beneficial AI Research, both focused on AI safety; known for identifying the "Basic AI Drives" framework widely cited in AI safety research. His contributions lend independent scientific rigor to the architecture.